//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
// Project    : Spartan-6 Integrated Block for PCI Express
// File       : board.v
// Description: Top level testbench
//
//-----------------------------------------------------------------------------

`timescale 1ns/1ns

`define RX_LOG                       0
`define TX_LOG                       1
`define TRN_RX_TIMEOUT               5000

module board;

  parameter          REF_CLK_FREQ       = 0;  // 0 - 100 MHz, 1 - 125 MHz

  localparam         REF_CLK_HALF_CYCLE = (REF_CLK_FREQ == 0) ? 5000 :
                                          (REF_CLK_FREQ == 1) ? 4000 : 0;

  localparam         AD_CLK_HALF_CYCLE  = 25_000;   // 20MHz, 50ns (50_000ps) per cycle.
  //
  // System reset
  //
  reg                sys_reset_n;

  //
  // System clocks
  //
  wire               rp_sys_clk;
  wire               ep_sys_clk_p;
  wire               ep_sys_clk_n;

  //
  // PCI-Express Serial Interconnect
  //
  wire               ep_pci_exp_txn;
  wire               ep_pci_exp_txp;
  wire               rp_pci_exp_txn;
  wire               rp_pci_exp_txp;

  wire               clk_20M;

  //
  // PCI-Express Endpoint Instance
  //

  xilinx_pcie_1_1_ep_s6 #(
    .FAST_TRAIN("TRUE")
  )
  EP (
    // SYS Inteface
    .sys_clk_p(ep_sys_clk_p),
    .sys_clk_n(ep_sys_clk_n),
    .sys_reset_n(sys_reset_n),

    // PCI-Express Interface
    .pci_exp_txn(ep_pci_exp_txn),
    .pci_exp_txp(ep_pci_exp_txp),
    .pci_exp_rxn(rp_pci_exp_txn),
    .pci_exp_rxp(rp_pci_exp_txp),

    .clk_20M(clk_20M),
    // Misc signals
    .led_0(led_0),
    .led_1(led_1),
    .led_2(led_2),
    .led_3()
  );

  //
  // PCI-Express Model Root Port Instance
  //
  xilinx_pcie_2_0_rport_v6 #(
    .REF_CLK_FREQ(REF_CLK_FREQ),
    .PL_FAST_TRAIN("TRUE"),
    .RX_LOG(`RX_LOG),
    .TX_LOG(`TX_LOG),
    .TRN_RX_TIMEOUT(`TRN_RX_TIMEOUT)
  )
  RP (
    // SYS Inteface
    .sys_clk(rp_sys_clk),
    .sys_reset_n(sys_reset_n),

    // PCI-Express Interface
    .pci_exp_txn(rp_pci_exp_txn),
    .pci_exp_txp(rp_pci_exp_txp),
    .pci_exp_rxn(ep_pci_exp_txn),
    .pci_exp_rxp(ep_pci_exp_txp)
  );

  sys_clk_gen  # (
    .halfcycle(REF_CLK_HALF_CYCLE),
    .offset(0)
  )
  CLK_GEN_RP (
    .sys_clk(rp_sys_clk)
  );

  sys_clk_gen_ds #(
    .halfcycle(REF_CLK_HALF_CYCLE),
    .offset(0)
  )
  CLK_GEN_EP (
    .sys_clk_p(ep_sys_clk_p),
    .sys_clk_n(ep_sys_clk_n)
  );

  sys_clk_gen # (
      .halfcycle( AD_CLK_HALF_CYCLE),
      .offset(0)
  ) inst(
      .sys_clk( clk_20M )
  );

  initial begin
    $display("[%t] : System Reset Asserted...", $realtime);
    sys_reset_n = 1'b0;

    repeat (500)
      @(posedge ep_sys_clk_p);

    $display("[%t] : System Reset De-asserted...", $realtime);
    sys_reset_n = 1'b1;
  end

  initial begin

    if ($test$plusargs ("dump_all")) begin

      `ifdef NCV // Cadence TRN dump

        $recordsetup("design=board",
                     "compress",
                     "wrapsize=100M",
                     "version=1",
                     "run=1");
        $recordvars();

      `elsif VCS //Synopsys VPD dump

        $vcdplusfile("board.vpd");
        $vcdpluson;
        $vcdplusglitchon;
        $vcdplusflush;

      `else

        // Verilog VC dump
        $dumpfile("board.vcd");
        $dumpvars(0, board);

      `endif // ModelSim dump is handled through simulate_mti.do script
    end
  end

`undef RX_LOG
`undef TX_LOG
`undef TRN_RX_TIMEOUT

endmodule // board
